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ICM_20948_REGISTERS.h
Go to the documentation of this file.
1/*
2
3This file contains a useful c translation of the datasheet register map
4
5*/
6
7#ifndef _ICM_20948_REGISTERS_H_
8#define _ICM_20948_REGISTERS_H_
9
10#include <stdint.h>
11
12#ifdef __cplusplus
13extern "C"
14{
15#endif /* __cplusplus */
16
17 typedef enum
18 {
19 // Generalized
21
22 // Gyroscope and Accelerometer
23 // User Bank 0
26 // Break
28 // Break
32 // Break
38 // Break
45 // Break
47 // Break
50 // Break
89 // Break
91 // Break
96 // Break
100 // Break
104 // Break
105 AGB0_REG_MEM_START_ADDR = 0x7C, // Hmm, Invensense thought they were sneaky not listing these locations on the datasheet...
106 AGB0_REG_MEM_R_W = 0x7D, // These three locations seem to be able to access some memory within the device
107 AGB0_REG_MEM_BANK_SEL = 0x7E, // And that location is also where the DMP image gets loaded
109
110 // Bank 1
114 // Break
118 // Break
121 // Break
124 // Break
127 // Break
129 // Break
131
132 // Bank 2
143 // Break
150 // Break
152 // Break
158 // Break
160
161 // Bank 3
186 // Break
188
189 // Magnetometer
191 // Break
192 M_REG_ST1 = 0x10,
200 // Break
205 } ICM_20948_Reg_Addr_e; // These enums are not needed for the user, so they stay in this scope (simplifies naming among other things)
206
207 // Type definitions for the registers
208 typedef struct
209 {
210 uint8_t WHO_AM_I;
212
213 typedef struct
214 {
215 uint8_t reserved_0 : 1;
216 uint8_t I2C_MST_RST : 1;
217 uint8_t SRAM_RST : 1;
218 uint8_t DMP_RST : 1;
219 uint8_t I2C_IF_DIS : 1;
220 uint8_t I2C_MST_EN : 1;
221 uint8_t FIFO_EN : 1;
222 uint8_t DMP_EN : 1;
224
225 typedef struct
226 {
227 uint8_t reserved_0 : 4;
228 uint8_t GYRO_CYCLE : 1;
229 uint8_t ACCEL_CYCLE : 1;
230 uint8_t I2C_MST_CYCLE : 1;
231 uint8_t reserved_1 : 1;
233
234 typedef struct
235 {
236 uint8_t CLKSEL : 3;
237 uint8_t TEMP_DIS : 1;
238 uint8_t reserved_0 : 1;
239 uint8_t LP_EN : 1;
240 uint8_t SLEEP : 1;
241 uint8_t DEVICE_RESET : 1;
243
244 typedef struct
245 {
246 uint8_t DISABLE_GYRO : 3;
247 uint8_t DIABLE_ACCEL : 3;
248 uint8_t reserved_0 : 2;
250
251 typedef struct
252 {
253 uint8_t reserved_0 : 1;
254 uint8_t BYPASS_EN : 1;
255 uint8_t FSYNC_INT_MODE_EN : 1;
256 uint8_t ACTL_FSYNC : 1;
257 uint8_t INT_ANYRD_2CLEAR : 1;
258 uint8_t INT1_LATCH_EN : 1;
259 uint8_t INT1_OPEN : 1;
260 uint8_t INT1_ACTL : 1;
262
263 typedef struct
264 {
265 uint8_t I2C_MST_INT_EN : 1;
266 uint8_t DMP_INT1_EN : 1;
267 uint8_t PLL_READY_EN : 1;
268 uint8_t WOM_INT_EN : 1;
269 uint8_t reserved_0 : 3;
270 uint8_t REG_WOF_EN : 1;
272
273 typedef struct
274 {
275 uint8_t RAW_DATA_0_RDY_EN : 1;
276 uint8_t reserved_0 : 7;
278
279 typedef union
280 {
281 struct
282 {
284 uint8_t reserved_0 : 3;
285 } grouped;
286 struct
287 {
293 uint8_t reserved_0 : 3;
294 } individual;
296
297 // typedef struct{
298 // uint8_t FIFO_OVERFLOW_EN_40 : 5;
299 // uint8_t reserved_0 : 3;
300 // }ICM_20948_INT_ENABLE_2_t;
301
302 typedef union
303 {
304 struct
305 {
306 uint8_t FIFO_WM_EN_40 : 5;
307 uint8_t reserved_0 : 3;
308 } grouped;
309 struct
310 {
311 uint8_t FIFO_WM_EN_0 : 1;
312 uint8_t FIFO_WM_EN_1 : 1;
313 uint8_t FIFO_WM_EN_2 : 1;
314 uint8_t FIFO_WM_EN_3 : 1;
315 uint8_t FIFO_WM_EN_4 : 1;
316 uint8_t reserved_0 : 3;
317 } individual;
319
320 // typedef struct{
321 // uint8_t FIFO_WM_EN_40 : 5;
322 // uint8_t reserved_0 : 3;
323 // }ICM_20948_INT_ENABLE_3_t;
324
325 typedef struct
326 {
327 uint8_t I2C_PERIPH0_NACK : 1;
328 uint8_t I2C_PERIPH1_NACK : 1;
329 uint8_t I2C_PERIPH2_NACK : 1;
330 uint8_t I2C_PERIPH3_NACK : 1;
331 uint8_t I2C_PERIPH4_NACK : 1;
332 uint8_t I2C_LOST_ARB : 1;
333 uint8_t I2C_PERIPH4_DONE : 1;
334 uint8_t PASS_THROUGH : 1;
336
337 typedef struct
338 {
339 uint8_t reserved0 : 1;
341 uint8_t reserved1 : 1;
343 uint8_t reserved2 : 4;
344 } ICM_20948_DMP_INT_STATUS_t; // Mostly guesswork from InvenSense App Note
345
346 typedef struct
347 {
348 uint8_t I2C_MST_INT : 1;
349 uint8_t DMP_INT1 : 1;
350 uint8_t PLL_RDY_INT : 1;
351 uint8_t WOM_INT : 1;
352 uint8_t reserved_0 : 4;
354
355 typedef struct
356 {
358 uint8_t reserved_0 : 7;
360
361 // typedef union{
362 // struct{
363 // uint8_t FIFO_OVERFLOW_INT_40 : 5;
364 // uint8_t reserved_0 : 3;
365 // }grouped;
366 // struct{
367 // uint8_t FIFO_OVERFLOW_INT_0 : 1;
368 // uint8_t FIFO_OVERFLOW_INT_1 : 1;
369 // uint8_t FIFO_OVERFLOW_INT_2 : 1;
370 // uint8_t FIFO_OVERFLOW_INT_3 : 1;
371 // uint8_t FIFO_OVERFLOW_INT_4 : 1;
372 // uint8_t reserved_0 : 3;
373 // }individual;
374 // }ICM_20948_INT_STATUS_2_t;
375
376 typedef struct
377 {
379 uint8_t reserved_0 : 3;
381
382 // typedef union{
383 // struct{
384 // uint8_t FIFO_WM_INT_40 : 5;
385 // uint8_t reserved_0 : 3;
386 // }grouped;
387 // struct{
388 // uint8_t FIFO_WM_INT_0 : 1;
389 // uint8_t FIFO_WM_INT_1 : 1;
390 // uint8_t FIFO_WM_INT_2 : 1;
391 // uint8_t FIFO_WM_INT_3 : 1;
392 // uint8_t FIFO_WM_INT_4 : 1;
393 // uint8_t reserved_0 : 3;
394 // }individual;
395 // }ICM_20948_INT_STATUS_3_t;
396
397 typedef struct
398 {
399 uint8_t FIFO_WM_INT40 : 5;
400 uint8_t reserved_0 : 3;
402
403 typedef struct
404 {
405 uint8_t DELAY_TIMEH;
407
408 typedef struct
409 {
410 uint8_t DELAY_TIMEL;
412
413 typedef struct
414 {
417
418 typedef struct
419 {
422
423 typedef struct
424 {
427
428 typedef struct
429 {
432
433 typedef struct
434 {
437
438 typedef struct
439 {
442
443 typedef struct
444 {
445 uint8_t GYRO_XOUT_H;
447
448 typedef struct
449 {
450 uint8_t GYRO_XOUT_L;
452
453 typedef struct
454 {
455 uint8_t GYRO_YOUT_H;
457
458 typedef struct
459 {
460 uint8_t GYRO_YOUT_L;
462
463 typedef struct
464 {
465 uint8_t GYRO_ZOUT_H;
467
468 typedef struct
469 {
470 uint8_t GYRO_ZOUT_L;
472
473 typedef struct
474 {
475 uint8_t TEMP_OUT_H;
477
478 typedef struct
479 {
480 uint8_t TEMP_OUT_L;
482
483 typedef struct
484 {
485 uint8_t DATA; // Note: this is not worth copying 24 times, despite there being 24 registers like this one
487
488 typedef struct
489 {
490 uint8_t PERIPH_0_FIFO_EN : 1;
491 uint8_t PERIPH_1_FIFO_EN : 1;
492 uint8_t PERIPH_2_FIFO_EN : 1;
493 uint8_t PERIPH_3_FIFO_EN : 1;
494 uint8_t reserved_0 : 4;
496
497 typedef struct
498 {
499 uint8_t TEMP_FIFO_EN : 1;
500 uint8_t GYRO_X_FIFO_EN : 1;
501 uint8_t GYRO_Y_FIFO_EN : 1;
502 uint8_t GYRO_Z_FIFO_EN : 1;
503 uint8_t ACCEL_FIFO_EN : 1;
504 uint8_t reserved_0 : 3;
506
507 typedef struct
508 {
509 uint8_t FIFO_RESET : 5;
510 uint8_t reserved_0 : 3;
512
513 typedef struct
514 {
515 uint8_t FIFO_MODE : 5;
516 uint8_t reserved_0 : 3;
518
519 typedef struct
520 {
521 uint8_t FIFO_COUNTH;
523
524 typedef struct
525 {
526 uint8_t FIFO_COUNTL;
528
529 typedef struct
530 {
531 uint8_t RAW_DATA_RDY : 4;
532 uint8_t reserved_0 : 3;
533 uint8_t WOF_STATUS : 1;
535
536 typedef struct
537 {
538 uint8_t FIFO_CFG : 1;
539 uint8_t reserved_0 : 7;
541
542 // User bank 1 Types
543
544 typedef struct
545 {
546 uint8_t XG_ST_DATA;
548
549 typedef struct
550 {
551 uint8_t YG_ST_DATA;
553
554 typedef struct
555 {
556 uint8_t ZG_ST_DATA;
558
559 typedef struct
560 {
561 uint8_t XA_ST_DATA;
563
564 typedef struct
565 {
566 uint8_t YA_ST_DATA;
568
569 typedef struct
570 {
571 uint8_t ZA_ST_DATA;
573
574 typedef struct
575 {
578
579 typedef struct
580 {
581 uint8_t reserved_0 : 1;
582 uint8_t XA_OFFS_6_0 : 7;
584
585 typedef struct
586 {
589
590 typedef struct
591 {
592 uint8_t reserved_0 : 1;
593 uint8_t YA_OFFS_6_0 : 7;
595
596 typedef struct
597 {
600
601 typedef struct
602 {
603 uint8_t reserved_0 : 1;
604 uint8_t ZA_OFFS_6_0 : 7;
606
607 typedef struct
608 {
609 uint8_t TBC_PLL;
611
612 // User Bank 2 Types
613 typedef struct
614 {
617
618 typedef struct
619 {
620 uint8_t GYRO_FCHOICE : 1;
621 uint8_t GYRO_FS_SEL : 2;
622 uint8_t GYRO_DLPFCFG : 3;
623 uint8_t reserved_0 : 2;
625
626 typedef struct
627 {
628 uint8_t GYRO_AVGCFG : 3;
629 uint8_t ZGYRO_CTEN : 1;
630 uint8_t YGYRO_CTEN : 1;
631 uint8_t XGYRO_CTEN : 1;
632 uint8_t reserved_0 : 2;
634
635 typedef struct
636 {
639
640 typedef struct
641 {
644
645 typedef struct
646 {
649
650 typedef struct
651 {
654
655 typedef struct
656 {
659
660 typedef struct
661 {
664
665 typedef struct
666 {
667 uint8_t ODR_ALIGN_EN : 1;
668 uint8_t reserved_0 : 7;
670
671 typedef struct
672 {
674 uint8_t reserved_0 : 4;
676
677 typedef struct
678 {
681
682 typedef struct
683 {
685 uint8_t ACCEL_INTEL_EN : 1;
686 uint8_t reserved_0 : 6;
688
689 typedef struct
690 {
693
694 typedef struct
695 {
696 uint8_t ACCEL_FCHOICE : 1;
697 uint8_t ACCEL_FS_SEL : 2;
698 uint8_t ACCEL_DLPFCFG : 3;
699 uint8_t reserved_0 : 2;
701
702 typedef struct
703 {
704 uint8_t DEC3_CFG : 2;
705 uint8_t AZ_ST_EN : 1;
706 uint8_t AY_ST_EN : 1;
707 uint8_t AX_ST_EN : 1;
708 uint8_t reserved_0 : 3;
710
711 typedef struct
712 {
713 uint8_t EXT_SYNC_SET : 4;
714 uint8_t WOF_EDGE_INT : 1;
715 uint8_t WOF_DEGLITCH_EN : 1;
716 uint8_t reserved_0 : 1;
717 uint8_t DELAY_TIME_EN : 1;
719
720 typedef struct
721 {
722 uint8_t TEMP_DLPFCFG : 3;
723 uint8_t reserved_0 : 5;
725
726 typedef struct
727 {
728 uint8_t REG_LP_DMP_EN : 1;
729 uint8_t reserved_0 : 7;
731
732 // Bank 3 Types
733
734 typedef struct
735 {
737 uint8_t reserved_0 : 4;
739
740 typedef struct
741 {
742 uint8_t I2C_MST_CLK : 4;
743 uint8_t I2C_MST_P_NSR : 1;
744 uint8_t reserved_0 : 2;
745 uint8_t MULT_MST_EN : 1;
747
748 typedef struct
749 {
755 uint8_t reserved_0 : 2;
756 uint8_t DELAY_ES_SHADOW : 1;
758
759 typedef struct
760 {
761 uint8_t ID : 7;
762 uint8_t RNW : 1;
764
765 typedef struct
766 {
767 uint8_t REG;
769
770 typedef struct
771 {
772 uint8_t LENG : 4;
773 uint8_t GRP : 1;
774 uint8_t REG_DIS : 1;
775 uint8_t BYTE_SW : 1;
776 uint8_t EN : 1;
778
779 typedef struct
780 {
781 uint8_t DO;
783
784 typedef struct
785 {
786 uint8_t DLY : 5;
787 uint8_t REG_DIS : 1;
788 uint8_t INT_EN : 1;
789 uint8_t EN : 1;
791
792 typedef struct
793 {
794 uint8_t DI;
796
797 // Bank select register!
798
799 typedef struct
800 {
801 uint8_t reserved_0 : 4;
802 uint8_t USER_BANK : 2;
803 uint8_t reserved_1 : 2;
805
806#ifdef __cplusplus
807}
808#endif /* __cplusplus */
809
810#endif /* _ICM_20948_REGISTERS_H_ */
ICM_20948_Reg_Addr_e
@ AGB1_REG_SELF_TEST_Y_ACCEL
@ AGB0_REG_FIFO_COUNT_H
@ AGB0_REG_MEM_BANK_SEL
@ AGB0_REG_INT_ENABLE_3
@ AGB3_REG_I2C_PERIPH2_REG
@ AGB0_REG_EXT_PERIPH_SENS_DATA_17
@ AGB0_REG_GYRO_YOUT_L
@ AGB3_REG_I2C_PERIPH3_CTRL
@ AGB0_REG_EXT_PERIPH_SENS_DATA_14
@ AGB0_REG_EXT_PERIPH_SENS_DATA_18
@ AGB1_REG_SELF_TEST_Z_ACCEL
@ REG_BANK_SEL
@ AGB0_REG_TEMP_OUT_L
@ AGB0_REG_FIFO_R_W
@ AGB0_REG_INT_ENABLE_2
@ AGB3_REG_I2C_PERIPH4_REG
@ AGB1_REG_SELF_TEST_X_ACCEL
@ AGB0_REG_INT_STATUS
@ AGB0_REG_PWR_MGMT_2
@ AGB0_REG_ACCEL_ZOUT_L
@ AGB0_REG_MEM_R_W
@ M_REG_CNTL2
@ AGB0_REG_INT_STATUS_1
@ AGB0_REG_PWR_MGMT_1
@ AGB0_REG_ACCEL_YOUT_L
@ AGB3_REG_I2C_MST_DELAY_CTRL
@ AGB0_REG_EXT_PERIPH_SENS_DATA_03
@ AGB0_REG_FIFO_EN_1
@ AGB2_REG_ODR_ALIGN_EN
@ AGB3_REG_I2C_PERIPH2_DO
@ AGB0_REG_GYRO_XOUT_H
@ AGB0_REG_INT_ENABLE_1
@ AGB0_REG_EXT_PERIPH_SENS_DATA_08
@ AGB3_REG_I2C_PERIPH1_DO
@ AGB0_REG_INT_PIN_CONFIG
@ AGB1_REG_ZA_OFFS_L
@ AGB0_REG_TEMP_CONFIG
@ AGB0_REG_REG_BANK_SEL
@ AGB0_REG_EXT_PERIPH_SENS_DATA_15
@ AGB3_REG_I2C_PERIPH2_ADDR
@ AGB1_REG_TIMEBASE_CORRECTION_PLL
@ AGB3_REG_I2C_PERIPH4_CTRL
@ AGB2_REG_GYRO_SMPLRT_DIV
@ AGB0_REG_EXT_PERIPH_SENS_DATA_11
@ AGB1_REG_YA_OFFS_L
@ AGB0_REG_FIFO_EN_2
@ AGB0_REG_DATA_RDY_STATUS
@ AGB3_REG_I2C_PERIPH4_DO
@ AGB3_REG_I2C_PERIPH1_CTRL
@ AGB0_REG_GYRO_XOUT_L
@ AGB2_REG_ZG_OFFS_USRH
@ AGB3_REG_I2C_PERIPH0_DO
@ AGB3_REG_I2C_PERIPH0_ADDR
@ AGB0_REG_HW_FIX_DISABLE
@ AGB1_REG_XA_OFFS_L
@ AGB0_REG_EXT_PERIPH_SENS_DATA_21
@ AGB2_REG_ACCEL_WOM_THR
@ AGB2_REG_MOD_CTRL_USR
@ AGB0_REG_GYRO_ZOUT_H
@ AGB0_REG_LPF
@ AGB3_REG_I2C_MST_CTRL
@ AGB0_REG_DMP_INT_STATUS
@ AGB3_REG_I2C_PERIPH3_ADDR
@ AGB0_REG_EXT_PERIPH_SENS_DATA_10
@ AGB0_REG_EXT_PERIPH_SENS_DATA_09
@ AGB0_REG_ACCEL_ZOUT_H
@ AGB0_REG_EXT_PERIPH_SENS_DATA_01
@ AGB0_REG_INT_STATUS_2
@ AGB2_REG_PRGM_START_ADDRH
@ AGB3_REG_I2C_PERIPH2_CTRL
@ AGB0_REG_INT_STATUS_3
@ AGB3_REG_I2C_PERIPH4_ADDR
@ AGB0_REG_FIFO_MODE
@ AGB0_REG_TEMP_OUT_H
@ AGB1_REG_XA_OFFS_H
@ AGB0_REG_EXT_PERIPH_SENS_DATA_19
@ AGB2_REG_XG_OFFS_USRL
@ AGB3_REG_I2C_PERIPH3_DO
@ AGB1_REG_SELF_TEST_Z_GYRO
@ AGB0_REG_EXT_PERIPH_SENS_DATA_22
@ AGB2_REG_PRS_ODR_CONFIG
@ AGB2_REG_ACCEL_INTEL_CTRL
@ AGB0_REG_FIFO_CFG
@ AGB3_REG_I2C_PERIPH1_REG
@ AGB2_REG_ZG_OFFS_USRL
@ AGB2_REG_ACCEL_SMPLRT_DIV_1
@ AGB2_REG_XG_OFFS_USRH
@ AGB0_REG_EXT_PERIPH_SENS_DATA_23
@ AGB0_REG_MEM_START_ADDR
@ AGB0_REG_GYRO_YOUT_H
@ AGB0_REG_GYRO_ZOUT_L
@ AGB0_REG_EXT_PERIPH_SENS_DATA_00
@ AGB0_REG_DELAY_TIMEH
@ AGB0_REG_WHO_AM_I
@ AGB3_REG_REG_BANK_SEL
@ AGB0_REG_INT_ENABLE
@ AGB3_REG_I2C_MST_ODR_CONFIG
@ AGB2_REG_PRGM_START_ADDRL
@ AGB0_REG_EXT_PERIPH_SENS_DATA_16
@ AGB2_REG_ACCEL_CONFIG_2
@ AGB1_REG_YA_OFFS_H
@ AGB0_REG_ACCEL_YOUT_H
@ AGB2_REG_YG_OFFS_USRH
@ AGB1_REG_ZA_OFFS_H
@ AGB0_REG_EXT_PERIPH_SENS_DATA_20
@ AGB2_REG_GYRO_CONFIG_2
@ AGB0_REG_EXT_PERIPH_SENS_DATA_07
@ AGB0_REG_I2C_MST_STATUS
@ AGB0_REG_LP_CONFIG
@ AGB2_REG_TEMP_CONFIG
@ AGB3_REG_I2C_PERIPH3_REG
@ AGB0_REG_EXT_PERIPH_SENS_DATA_04
@ AGB0_REG_DELAY_TIMEL
@ AGB0_REG_FIFO_RST
@ M_REG_CNTL3
@ AGB0_REG_USER_CTRL
@ AGB0_REG_EXT_PERIPH_SENS_DATA_12
@ AGB2_REG_ACCEL_SMPLRT_DIV_2
@ AGB3_REG_I2C_PERIPH0_CTRL
@ AGB2_REG_YG_OFFS_USRL
@ AGB0_REG_EXT_PERIPH_SENS_DATA_13
@ AGB2_REG_FSYNC_CONFIG
@ AGB1_REG_SELF_TEST_X_GYRO
@ AGB3_REG_I2C_PERIPH1_ADDR
@ AGB3_REG_I2C_PERIPH4_DI
@ AGB0_REG_EXT_PERIPH_SENS_DATA_02
@ AGB2_REG_ACCEL_CONFIG
@ AGB0_REG_FIFO_COUNT_L
@ AGB2_REG_GYRO_CONFIG_1
@ AGB0_REG_ACCEL_XOUT_H
@ AGB0_REG_ACCEL_XOUT_L
@ AGB0_REG_EXT_PERIPH_SENS_DATA_06
@ AGB1_REG_REG_BANK_SEL
@ AGB0_REG_EXT_PERIPH_SENS_DATA_05
@ AGB1_REG_SELF_TEST_Y_GYRO
@ AGB3_REG_I2C_PERIPH0_REG
@ AGB0_REG_SINGLE_FIFO_PRIORITY_SEL
@ AGB2_REG_REG_BANK_SEL